Hi Gents,

I'm in a meeting so I'll try to keep (unusually) brief! :-)

Firstly, I think I'm wrong on Xmas being a higher bandwidth version of the digitally controlled PLL. Just wanted to get that out of the way. The 568 diags screen seems to contradict this.

I think that it's confusing that the players, speakers and processors all use the same term FIFO dejittering. The following is speculation (just like the original exchange).

The speakers and processors have a FIFO. The speakers probably have a smaller one, or are not allowed to use as much for reasons that Joel spotted. This FIFO stores incoming data at its own rate, and outputs data at the on board voltage controlled oscillator (VCO) rate. This bit is important. The FIFO is just a buffer, it can't dejitter on its own. It's just there as somewhere to hold the data whilst the clocks differ. The frequency of the VCO is controlled such to keep the buffer about half full. Or half empty if you're into HD DVD :-) By making these changes slowly, you reduce jitter. The speakers will have to change more quickly than the processor.

The FIFO on the players will be different. This time there is control over the speed of the source. That's the key difference to the processors - flow control. I'd bet that this time the oscillator is not voltage controlled. It will probably be a fixed high precision oscillator. This time the jitter is just dependent on the quality of the oscillator, power supply decoupling around it and clock distribution. There is no PLL (unless there's on board clean up of the oscillator), no VCO and no bandwidth. To keep the FIFO half full this time, you vary the speed at which you take the data. The circuit and behaviour is completely different to the processors, but they both need FIFO buffers.

The difference is that the feedback loop is related to the output jitter in the processor's case. In the player's case it just controls the speed of the drive (indirectly).

If this is true, then perhaps the one piece player/processors have the lowest jitter of all? Unless something special was done with speakerlink and we're about to see cat-5 inputs on the 861.

One more thought, although I have said it in the past, FIFO dejittering is not technically a special case of PLL, but it is so close not to matter in this case. The output clock is not phase aligned to the input. The output data rate is nominally matched. We don't care about phase matching it. The concepts of feedback, bandwidth and VCOs all apply in exactly the same manner.

So much for brevity!

Cheers,

Mark.

861v8, DSP5200, DSP5200HC, DSP5000mk2, UHD722, MF10, Prime, Prime PSU