Hi,

As the writer of the passage quoted, I think I should clarify what I said. As one poster mentioned, a clearer way of stating it is that upsampling may alter jitter characteristics in a favorable way relative to 44.1kHz. However, like anything else, it can also degrade the signal, and it all depends on the particular details of the implementation.

For example, many DACs these days use a Sample-Rate Converter (SRC) to do their upsampling. The architecture of the SRC affects its response to jitter. The Analog Devices AD1862 SRC popular a few years ago would convert jitter into a higher noise floor rather than FM-modulated components, leading, theoretically, to a more benign, less audible response to a jittery signal. Incidentally, tests done on the Meridian 518 indicates that it does something similar to that, though I don't think it uses an SRC.

As for the SPDIF architecture being inherently flawed, I think, while that may be possible, that is but one component of a device's performance in the real world. Other things that can affect it as well, which some jitter boxes fixe inadvertently also fix are:

1. Resistance to common-mode RF noise, both airborne and conducted. Many jitter boxes actually improve this because they commonly have some kind of pulse transformer at their digial inputs and outputs. The Z-Systems RDP-1 and RDQ-1 digital preamps and EQs do this quite well because their SPDIF interfaces are exceedingly well-designed with respect to this. Things that may help in this category include:

a. good shielded cabling

b. good interface to the chassis, which is properly grounded. A BNC plug with a circumferential bypass cap to ground and circumferential termination of the ground to chassis is a good start.

c. input and output transformers with appropriate filtering: low inductance, low reactance at the appropriate frequencies.

d. good conductive chassis with screws no further apart or openings not larger than 1/4 of the wavelength of the highest frequency your circuit will react to.

2. Good internal circuit design:

a. surface-mount components throughout, especially bypass caps for high-frequency components (all digital chips, high opne-loop bandwidth op-amps, etc.). The components must be of low-inductance and low-reactivity, ideally resistive up to the upper limits of their working frequency range.

b. multi-layer board of at least 4 layers with complete ground planes, and good layout. This includes routing high-frequency currents on the ground plane correctly, mounting of chips directly to the board with appropriate shielding on the board and perhaps around the chip, and taking into account the high-frequency impedance of traces when transmitting signals.

3. Good handling of the analog interface, which means only correctly balanced I/O, with analog shields circumferentially attached to chassis only, and balanced operation up to upper limits of analog working frequencies (meaning upper end of open-loop bandwidth of amps in the analog section). To get balanced signals, an output transformer is best, but a passive balancer (matching impedance to ground of pins 1 and 2 with resistors, inductors, capacitors) is fine, too.

I don't think I've seen any one component with all of these things, except perhaps for the Z-Systems stuff. The TAG McLaren AV32R is very good in many of these respects. Meridian's pretty good too.

--Andre